Interval-based clock synchronization with optimal precision

AbstractWe present description and analysis of a novel optimal precision clock synchronization algorithm (OP), which takes care of both precision and accuracy with respect to external time. It relies upon the generic interval-based algorithm of Schmid and Schossmaier [Real-Time Syst. 12 (2) (1997) 173] and utilizes a convergence function based on the orthogonal accuracy algorithm of Schmid [Chicago J. Theor. Comput. Sci. 3 (2000) 3]. As far as precision is concerned, we show that OP achieves optimal worst case precision, optimal maximum clock adjustment, and optimal rate, as does the algorithm of Fetzer and Cristian [Proceedings 10th Annual IEEE Conference on Computer Assurance, Gaithersburg, MD, 1995]. However, relying upon a perception-based hybrid fault model and a fairly realistic system model, our results are valid for a wide variety of node and link faults and apply to very high-precision applications as well: Impairments due to clock granularity and discrete rate adjustment cannot be ignored here anymore. Our accuracy analysis focuses on the nodes’ local accuracy interval, which provides the atop running application with an on-line bound on the current deviation from external time. We show that this bound could get larger than twice the necessary lower bound (“traditional accuracy”), hence OP is considerably suboptimal in this respect

An Interval-based Framework for Clock Rate Synchronization

This paper addresses the problem of synchronizing the rate of clocks in a fault-tolerant distributed system. Contrived to bring the rates of all non-faulty clocks in accordance, rate synchronization algorithms are very similar to usual "state" synchronization ones. Major differences, however, arise from the fact that the quantities to be synchronized are not directly accessible and that they do not proceed linearly with time. Relying on an interval-based paradigm, we introduce a basic system model and suitable building blocks for a generic rate synchronization algorithm that employs a convergence function. Our rigorous analysis of the mutual rate deviation (aka. consonance) and deviation from the ideal rate of 1 Sec/sec (aka. drift) reveals that the clock rate stability (i.e. the maximum rate change per unit of time) takes over the role of maximum hardware drift rate in traditional clock synchronization approaches. Keywords: distributed systems, clock synchronization, drift, consonanc..

NTI: A Network Time Interface M-Module for High-Accuracy Clock Synchronization

This paper 1 provides a description of our Network Time Interface M-Module (NTI) supporting very-high accuracy external clock synchronization by hardware. The NTI is built around our custom Universal Time Coordinated Synchronization Unit VLSI chip (UTCSUASIC) , which contains the core of the hardware support required for interval-based clock synchronization: A state and rate adjustable clock device, locally maintained accuracy intervals, interfaces to GPS receivers, and various timestamping features. Designed for maximum network and CPU independence, our NTI provides a turn-key solution for adding highresolution synchronized clocks to distributed real-time systems built upon hardware with M-Module interfaces. Keywords: external clock synchronization, hardware support, fault-tolerant distributed real-time systems, interval-based paradigm, M-Modules, GPS, VLSI. 1 Introduction Designing distributed fault-tolerant real-time applications is usually considerably simplified when..

How to Reconcile Fault-Tolerant Interval Intersection with the Lipschitz Condition

this paper satisfies a Lipschitz condition and takes into account the widths of intervals. Since F is in fact optimal among all such functions, we can reasonably claim to have settled Lamport's questio

An ASIC Supporting External Clock Synchronization for Distributed Real-Time Systems

Designing clock synchronization algorithms for distributed real-time systems based on packet networks requires to decide on the amount and functionality of proper hardware support. Targeting a 1¯s precision and similar accuracy measures in case of external UTC supply from GPS-receivers, this paper describes pertinent features of a peripheral device called UTCSU manufactured as an ASIC. The most salient one is the introduction of an adder-based clock, that allows a fine grained rate adjustment, continuous amortization, and maintenance of local accuracy intervals. Keywords: External clock synchronization, Universal Time Coordinated (UTC), Application Specific Integrated Circuit (ASIC), Very high speed integrated circuit Hardware Description Language (VHDL), Global Positioning System (GPS), Adder-based Clock. 1 Hardware Requirements A time service of a distributed real-time system comprises a set of nodes each hosting a physical clock, and some communication subsystem to exchange packet..

Interval-based Clock Synchronization Revisited

This report provides a few extensions and additions to the generic analysis of interval-based clock synchronization conducted in [SS97]. Apart from adding traditional accuracy and global rate to the major theorem, the accuracy analysis has been modified to circumvent the overly conservative bounds provided by the original framework

Specification and Implementation of the Universal Time Coordinated Synchronization Unit (UTCSU)

. High accurate external clock synchronization can only be achieved with adequate hardware support. We analyze the requirements yielding a specification and implementation of an ASIC running under the acronym UTCSU. It incorporates adder-based clocks to maintain both local time and accuracy, facilities to timestamp packets containing synchronization data, interfaces to couple GPS receivers, moderate application support, and self-test machinery. These novel clocks are distinguished by their fine grained rate adjustability and their hardware support for linear continuous amortization. Apart from addressing design and engineering issues of this chip, the paper provides a basic programming model as well. Keywords: Real-time systems, external clock synchronization, Universal Time Coordinated (UTC), adder-based clock (ABC), linear continuous amortization, accuracy intervals, Application Specific Integrated Circuit (ASIC), Very high speed integrated circuit Hardware Description Language (VHD..

PSynUTC—evaluation of a high precision time synchronization prototype system for ethernet lans

This article presents an overview and some evaluation results of our PSynUTC 1 prototype system for GPS time distribution and time synchronization in Ethernetbased LANs. PSynUTC does not need dedicated GPS receivers at every computing node but uses ordinary data packets for disseminating time information. High accuracy is achieved by combining (1) hardware packet timestamping at the network interface of nodes and switches, (2) high-resolution, high-frequency adder-based clocks with superior adjustment capabilities, and (3) clock rate synchronization algorithms compensating typical TCXO drifts. Our technology can be employed with any network controller chipset that supports the media-independent interface (MII) standard. Moreover, standard device drivers and protocol stacks can be used without any change. Our evaluation results show that PSynUTC will achieve a worst case synchronization accuracy in the 100 ns range, which is an improvement of at least 4 orders of magnitude over conventional software-based approaches like NTP.

A Unified Approach for Simulation and Experimental Evaluation of Fault-Tolerant Distributed Systems

This paper 1 surveys our framework for simulation and experimental evaluation of round-based clock synchronization algorithms in fault-tolerant distributed real-time systems. Developed in our project SynUTC, our toolkit is based upon a generic architecture that incorporates either real network controllers and clock devices or, alternatively, their simulated counterparts. Despite the higher design complexity, we obtained a considerable saving w.r.t. overall development time due to the fact that major parts of the toolkit, like data capture/analysis, are the same for both simulation and evaluation. We briefly outline the appropriate features and round off by a few sample results gathered from the simulation of two clock synchronization algorithms. Keywords: discrete event simulation, clock synchronization, fault-tolerant distributed real-time systems, data visualization, performance evaluation. 1 Motivation Dealing with distributed algorithms for fault-tolerant realtime systems us..

SynUTC—High Precision Time Synchronization over Ethernet Networks

This article describes our SynUTC * (Synchronized Universal Time Coordinated) technology, which enables highaccuracy distribution of GPS time and time synchronization of network nodes connected via standard Ethernet LANs. By means of exchanging data packets in conjunction with moderate hardware support at nodes and switches, an overall worst-case accuracy in the range of some 100 ns can be achieved, with negligible communication overhead. Our technology thus improves the 1 ms-range accuracy achievable by conventional, software-based approaches like NTP by 4 orders of magnitude. Applications can use the high-accuracy global time provided by SynUTC for event timestamping and event generation both at hardware and software level. SynUTC is based upon inserting highly accurate time information into dedicated data packets at the mediaindependent interface (MII) between the physical laye